HDL Design for Peta Hertz Clock Based 2e7-1 Peta Bits Per Second (P.b.p.s) - PRBS IP Core Generator For Ultra High Speed Wireless Products

Author's Name: Prof.P.N.V.M Sastry, Prof.Dr.D.N.Rao & Dr.S.Vathsal
Subject Area: Science and Engineering
Subject Energy
Section Research Paper


CCITT – Consulting Committee for International Telegraph & Telecom , ITU – International Telecom Unit, RTL- Register Transfer Level, LFSR-Linear Feedback Shift Register, VHDL- Very High Speed Integrated Circuit Hardware Description Language, PRBS-Pseudo Random Binary Sequence.


The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of 1 Peta Bits Per Second Pbps Data Rate using 2e7-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.

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